On Wed, Jul 05, 2023 at 09:03:23PM +0200, Andreas Kemnade wrote: > + /* probably no mclk if not master, so rely on bitclk */ > + if (!aic3x->master) > + clk_id = 2; > + This is fairly clearly a massive hack, we're just silently ignoring the clock we were asked to configure and choosing another one which is likely at a different rate to that we were expecting and sadly the driver didn't provide an automatic mode due to how old it is. We also appear to try to use the configured clock rate during PLL setup which still happens in hw_params() even with this change which is a bit of a concern here. Are you sure hw_params ends up doing the right thing, and that there are no other systems that get broken by this (perhaps ones sending a lower BCLK for example)? It would be nicer to set the clock via the DT bindings, ideally with the clock bindings...
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