Hi, * Andreas Kemnade <andreas@xxxxxxxxxxxx> [230119 21:16]: > I tried this hack-fix: > > --- a/sound/soc/ti/omap-mcbsp.c > +++ b/sound/soc/ti/omap-mcbsp.c > @@ -64,7 +64,7 @@ static int omap2_mcbsp_set_clks_src(struct omap_mcbsp *mcbsp, u8 fck_src_id) > if (fck_src_id == MCBSP_CLKS_PAD_SRC) > src = "pad_fck"; > else if (fck_src_id == MCBSP_CLKS_PRCM_SRC) > - src = "prcm_fck"; > + src = "mcbsp2_sync_mux_ck"; > else > return -EINVAL; > > > Then I stumple upon the next problem: > omap-mcbsp 40124000.mcbsp: CLKS: could not clk_set_parent() to mcbsp2_sync_mux_ck I don't think it's the direct parent here, the clkctrl clock bit 0 has the clksel parent at bits [25:24], and the clksel internal clock parent is bits [27:26]. See omap4_func_mcbsp2_gfclk_parents[] and omap4_mcbsp2_bit_data[]. I'd just use assigned-clock-parents on the internal clock, and possibly also for the clksel clock in the board specific dts file. This way the mcbsp driver doing pm_runtime_enable() will enable the clkctrl modulemode and the rest of the clock configuration should happen automatically. Regards, Tony
