On Mon, 15 Nov 2021 23:39:16 -0800, Parshuram Raju Thombare wrote:
> From: Parshuram Thombare <pthombar@xxxxxxxxxxx>
>
> Clear FLR (Function Level Reset) from device capabilities
> registers for all physical functions.
>
> During FLR, the Margining Lane Status and Margining Lane Control
> registers should not be reset, as per PCIe specification.
> However, the controller incorrectly resets these registers upon FLR.
> This causes PCISIG compliance FLR test to fail. Hence preventing
> all functions from advertising FLR support if flag quirk_disable_flr
> is set.
>
> [...]
Applied to pci/cadence, thanks!
[1/1] PCI: cadence: Clear FLR in device capabilities register
https://git.kernel.org/lpieralisi/pci/c/d3dbd4d862
Thanks,
Lorenzo
