Hi Nishanth Menon,
On Fri, 12 Nov 2021 22:36:35 -0600, Nishanth Menon wrote:
> A53's L2 cache[1] on AM642[2] is 256KB. A53's L2 is fixed line length
> of 64 bytes and 16-way set-associative cache structure.
>
> 256KB of L2 / 64 (line length) = 4096 ways
> 4096 ways / 16 = 256 sets
>
> Fix the l2 cache-sets.
>
> [...]
I have applied the following to branch ti-k3-dts-next on [1].
Thank you!
[1/1] arm64: dts: ti: k3-am642: Fix the L2 cache sets
commit: a27a93bf70045be54b594fa8482959ffb84166d7
All being well this means that it will be integrated into the linux-next
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[1] https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux.git
--
Vignesh
