Hi Nishanth Menon,
On Fri, 12 Nov 2021 22:36:38 -0600, Nishanth Menon wrote:
> A72's L2 cache[1] on J7200[2] is 1MB. A53's L2 is fixed line length of
> 64 bytes and 16-way set-associative cache structure.
>
Replaced A53 referenc with A72 locally and applied.
> 1MB of L2 / 64 (line length) = 16384 ways
> 16384 ways / 16 = 1024 sets
>
> Fix the l2 cache-sets.
>
> [...]
I have applied the following to branch ti-k3-dts-next on [1].
Thank you!
[1/1] arm64: dts: ti: k3-j7200: Fix the L2 cache sets
commit: d0c826106f3fc11ff97285102b576b65576654ae
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[1] https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux.git
--
Vignesh
