On 12/11/21 10:26PM, Nishanth Menon wrote: > A72 Cluster (chapter 1.3.1 [1]) has 48KB Icache, 32KB Dcache and 1MB L2 Cache > - ICache is 3-way set-associative > - Dcache is 2-way set-associative > - Line size are 64bytes > > 32KB (Dcache)/64 (fixed line length of 64 bytes) = 512 ways > 512 ways / 2 (Dcache is 2-way per set) = 256 sets. > > So, correct the d-cache-sets info. > > [1] https://www.ti.com/lit/pdf/spruiu1 > > Fixes: d361ed88455f ("arm64: dts: ti: Add support for J7200 SoC") > Reported-by: Peng Fan <peng.fan@xxxxxxx> > Signed-off-by: Nishanth Menon <nm@xxxxxx> Reviewed-by: Pratyush Yadav <p.yadav@xxxxxx> -- Regards, Pratyush Yadav Texas Instruments Inc.
