On 13/11/21 8:13 am, Nishanth Menon wrote: > A72 Cluster (chapter 1.3,1 [1]) has 48KB Icache, 32KB Dcache and 1MB L2 Cache > - ICache is 3-way set-associative > - Dcache is 2-way set-associative > - Line size are 64bytes > > 32KB (Dcache)/64 (fixed line length of 64 bytes) = 512 ways > 512 ways / 2 (Dcache is 2-way per set) = 256 sets. > > So, correct the d-cache-sets info. > > [1] https://www.ti.com/lit/pdf/spruiu1 > > Fixes: d361ed88455f ("arm64: dts: ti: Add support for J7200 SoC") > Reported-by: Peng Fan <peng.fan@xxxxxxx> > Signed-off-by: Nishanth Menon <nm@xxxxxx> Reviewed-by: Kishon Vijay Abraham I <kishon@xxxxxx> > --- > arch/arm64/boot/dts/ti/k3-j7200.dtsi | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/arch/arm64/boot/dts/ti/k3-j7200.dtsi b/arch/arm64/boot/dts/ti/k3-j7200.dtsi > index 47567cb260c2..958587d3a33d 100644 > --- a/arch/arm64/boot/dts/ti/k3-j7200.dtsi > +++ b/arch/arm64/boot/dts/ti/k3-j7200.dtsi > @@ -62,7 +62,7 @@ cpu0: cpu@0 { > i-cache-sets = <256>; > d-cache-size = <0x8000>; > d-cache-line-size = <64>; > - d-cache-sets = <128>; > + d-cache-sets = <256>; > next-level-cache = <&L2_0>; > }; > > @@ -76,7 +76,7 @@ cpu1: cpu@1 { > i-cache-sets = <256>; > d-cache-size = <0x8000>; > d-cache-line-size = <64>; > - d-cache-sets = <128>; > + d-cache-sets = <256>; > next-level-cache = <&L2_0>; > }; > }; >
