Jarkko Nikula [jhnikula@xxxxxxxxx] wrote: > Are you sure this change is necessary? CLKSRG is kind of master clock > to McBSP so original stetson guessed (?) 100 us should be fine for all > serial links where bit clock is higher than 20 kHz. The McBSP / DMA stuff doesn't really work properly, when PM is enabled to full extent. The first DMA goes in _before_ the omap_mcbsp_start(), so the higher delay compensates DMA misbehavior in a way... .. L/R channels also may switch at random initially with full PM enabled. So the L/R fix is only working, if no PM is enabled (sigh). Need to make that work fine (no L/R switching and early no DMA completions) to get rid of the higher, 500us, timeout. Maybe try not having XCCR/RCCR dma enable bit initially, but enabling them at omap_mcbsp_start()? (I'd try if I wasn't also on vacation). - Eero-- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
