Patch series adds support for legacy interrupt in pci-j721e. There are two HW implementations of legacy interrupt controller, one specific to J721E and the other for J7200/AM64. In both these implementations, the legacy interrupt is connect to pulse interrupt of GIC and level to pulse is handled by configuring EOI register. EOI to convert level to pulse is broken in J721E due to an errata but is functional in J7200. v1 of the patch series can be found @ [1] Patch series is created on top of [2] Changes from v1: 1) Only the legacy interrupt specific part is sent as part of this series. Rest are split and sent as a separate series [2] 2) Created irq_chip for legacy interrupt and used it's ops for enabling, disabling the interrupts. [1] -> http://lore.kernel.org/r/20210325090936.9306-1-kishon@xxxxxx [2] -> http://lore.kernel.org/r/20210803074932.19820-1-kishon@xxxxxx Kishon Vijay Abraham I (3): dt-bindings: PCI: ti,j721e: Add bindings to specify legacy interrupts PCI: j721e: Add PCI legacy interrupt support for J721E PCI: j721e: Add PCI legacy interrupt support for J7200 .../bindings/pci/ti,j721e-pci-host.yaml | 15 ++ drivers/pci/controller/cadence/pci-j721e.c | 150 ++++++++++++++++++ 2 files changed, 165 insertions(+) -- 2.17.1
