Hi, On 31/05/21 18:22, Pali Rohár wrote: > Hello Kishon! > > On Monday 31 May 2021 21:30:30 Kishon Vijay Abraham I wrote: >> I had given the timing mentioned in the specification here >> https://lore.kernel.org/r/023c9b59-70bb-ed8d-a4c0-76eae726b574@xxxxxx >> >> The PCI EXPRESS CARD ELECTROMECHANICAL SPECIFICATION defines the Power >> Sequencing and Reset Signal Timings in Table 2-4. Please also refer Figure >> 2-10: Power Up of the CEM. >> >> ╔═════════════╤══════════════════════════════════════╤═════╤═════╤═══════╗ >> ║ Symbol │ Parameter │ Min │ Max │ Units ║ >> ╠═════════════╪══════════════════════════════════════╪═════╪═════╪═══════╣ >> ║ T PVPERL │ Power stable to PERST# inactive │ 100 │ │ ms ║ >> ╟─────────────┼──────────────────────────────────────┼─────┼─────┼───────╢ >> ║ T PERST-CLK │ REFCLK stable before PERST# inactive │ 100 │ │ μs ║ >> ╟─────────────┼──────────────────────────────────────┼─────┼─────┼───────╢ >> ║ T PERST │ PERST# active time │ 100 │ │ μs ║ >> ╟─────────────┼──────────────────────────────────────┼─────┼─────┼───────╢ >> ║ T FAIL │ Power level invalid to PERST# active │ │ 500 │ ns ║ >> ╟─────────────┼──────────────────────────────────────┼─────┼─────┼───────╢ >> ║ T WKRF │ WAKE# rise – fall time │ │ 100 │ ns ║ >> ╚═════════════╧══════════════════════════════════════╧═════╧═════╧═══════╝ >> >> The de-assertion of #PERST is w.r.t both power stable and refclk stable. > > I think this does not fully answer this problematic question. One thing > is initial power on and second thing is warm reset (when both power and > clock is stable). > > On more ARM boards, power is not SW controllable and is automatically > enabled when powering board on. So Tₚᵥₚₑᵣₗ is calculated since > bootloader and therefore not needed to take into account in kernel. > > Tₚₑᵣₛₜ₋cₗₖ is only 100 µs and experiments proved that 100 µs not enough > for toggling PERST# GPIO. At least one 1 ms is needed and for some cards > at least 10 ms. Otherwise cards are not detected. > > So when you have both power and clock stable and you want to reset card > via PERST# signal, above table does not say how long it is needed to > have PERST# in reset state. Nothing happened after a few weeks... I understand that knowing the correct reset timings is relevant, but unfortunately I cannot help much in finding out the correct values. However I'm wondering what should happen to this patch. It *does* fix a real bug, but potentially with an incorrect or non-optimal usleep range. Do we really want to ignore a bugfix because we are not sure about how long this delay should be? -- Luca
