Hi, On 5/28/21 11:09 AM, Tony Lindgren wrote: > Hi Greg, Vignesh & Jan, > > * Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx> [210513 14:17]: >> On Tue, May 11, 2021 at 08:49:55PM +0530, Vignesh Raghavendra wrote: >>> It is possible that RX TIMEOUT is signalled after RX FIFO has been >>> drained, in which case a dummy read of RX FIFO is required to clear RX >>> TIMEOUT condition. Otherwise, RX TIMEOUT condition is not cleared >>> leading to an interrupt storm >>> >>> Cc: stable@xxxxxxxxxxxxxxx >> >> How far back does this need to go? What commit id does this fix? What >> caused this to just show up now vs. previously? Sorry, I missed this reply. Issue was reported on AM65x SoC with custom test case from Jan Kiszka that stressed UART with rapid baudrate changes from 9600 to 4M along with data transfer. Based on the condition that led to interrupt storm, I inferred it to affect all SoCs with 8250 OMAP UARTs. But that seems thats not the best idea as seen from OMAP3 regression. Greg, Could you please drop the patch? Very sorry for the inconvenience.. > > I just noticed this causes the following regression in Linux next when > pressing a key on uart console after boot at least on omap3. This seems > to happen on serial_port_in(port, UART_RX) in the quirk handling. > > Vignesh, it seems this quirk needs some soc specific flag added to > it maybe? Or maybe UART_OMAP_RX_LVL register is not available for > all the SoCs? > Yes indeed :( > I think it's best to drop this patch until the issues are resolved, > also there are some open comments above that might be answered by > limiting this quirk to a specific range of SoCs :) > Oops, I did test patch AM33xx assuming its equivalent to OMAP3, but UART IP is quite different. I will respin the patch making sure, workaround applies only to AM65x and K3 SoCs. Regards Vignesh
