RE: Camera Interface VS/HS Issue

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> -----Original Message-----
> From: linux-omap-owner@xxxxxxxxxxxxxxx [mailto:linux-omap-
> owner@xxxxxxxxxxxxxxx] On Behalf Of matthias schwarz
> Sent: Monday, July 27, 2009 7:47 AM
> To: linux-omap@xxxxxxxxxxxxxxx
> Subject: Camera Interface VS/HS Issue
> 
> Hi there,
> 
> i just recently ran into a problem when trying to let the ISP
> (OMAP3530) generate HS/VS signals in SYNC mode.
> I am building a module to do so.
> 
> It basically enables the three clocks (cam_ick, cam_mclk and
> csi2_96m_fck),
> then sets
> 
> ISPCCDC_PIX_LINES_PPLN
> ISPCCDC_PIX_LINES_HLPRF
> ISPCCDC_HD_VD_WID_VDW
> ISPCCDC_HD_VD_WID_HDW
> ISPCCDC_SYN_MODE_VDHDEN
> ISPCCDC_SYN_MODE_VDHDOUT
> ISPCCDC_CFG_VDLC
> ISPTCTRL_CTRL_DIVA
> ISPTCTRL_CTRL_DIVB
> ISPCCDC_PCR
> 
> via some calls to ioremap and ioread32/iowrite32.
> My question now is the following:
> when i hook an oscilloscope to the corresponding pins (CAM_VS, CAM_HS,
> CAM_XCLKA) i can see that only the CAM_XCLKA is working correctly,
> also at the configured frequency.
> Both, CAM_VS and CAM_HS remain at low voltage all the time, even when
> i switch their polarities (ISPCCDC_SYN_MODE_VDPOL,
> ISPCCDC_SYN_MODE_HDPOL) that behavior does not change and signals
> always remain at low voltage.
> 
> Could someone help me out, or give me a hint what i might be missing
> to generate those output signals correctly?

Matthias,

Can you please provide a register dump of the above values?

Looks like you're touching the adequate registers though... But I can help you more looking at the values.

Regards,
Sergio
> 
> Thank you very much,
> Matthias
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