On Mon, Nov 16, 2020 at 11:01:39PM +0530, Kishon Vijay Abraham I wrote: > Fix binding documentation of "ti,syscon-pcie-ctrl" to take phandle with > argument. The argument is the register offset within "syscon" used to > configure PCIe controller. > > Link: Link: http://lore.kernel.org/r/CAL_JsqKiUcO76bo1GoepWM1TusJWoty_BRy2hFSgtEVMqtrvvQ@xxxxxxxxxxxxxx Link: Link: ? AIUI, 'Link' is supposed to be a link to this patch. I guess more than 1 Link would be okay though. > Signed-off-by: Kishon Vijay Abraham I <kishon@xxxxxx> > --- > .../devicetree/bindings/pci/ti,j721e-pci-ep.yaml | 12 ++++++++---- > .../devicetree/bindings/pci/ti,j721e-pci-host.yaml | 12 ++++++++---- > 2 files changed, 16 insertions(+), 8 deletions(-) > > diff --git a/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml b/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml > index 3ae3e1a2d4b0..e9685c0bdc3e 100644 > --- a/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml > +++ b/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml > @@ -29,9 +29,13 @@ properties: > - const: mem > > ti,syscon-pcie-ctrl: > - description: Phandle to the SYSCON entry required for configuring PCIe mode > - and link speed. > - $ref: /schemas/types.yaml#/definitions/phandle > + allOf: You no longer need allOf here. > + - $ref: /schemas/types.yaml#/definitions/phandle-array > + - items: > + - items: > + - description: Phandle to the SYSCON entry > + - description: pcie_ctrl register offset within SYSCON > + description: Specifier for configuring PCIe mode and link speed. > > power-domains: > maxItems: 1 > @@ -80,7 +84,7 @@ examples: > <0x00 0x0d000000 0x00 0x00800000>, > <0x00 0x10000000 0x00 0x08000000>; > reg-names = "intd_cfg", "user_cfg", "reg", "mem"; > - ti,syscon-pcie-ctrl = <&pcie0_ctrl>; > + ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x4070>; > max-link-speed = <3>; > num-lanes = <2>; > power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>; > diff --git a/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml b/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml > index ee7a8eade3f6..a3b82992bcfa 100644 > --- a/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml > +++ b/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml > @@ -29,9 +29,13 @@ properties: > - const: cfg > > ti,syscon-pcie-ctrl: > - description: Phandle to the SYSCON entry required for configuring PCIe mode > - and link speed. > - $ref: /schemas/types.yaml#/definitions/phandle > + allOf: > + - $ref: /schemas/types.yaml#/definitions/phandle-array > + - items: > + - items: > + - description: Phandle to the SYSCON entry > + - description: pcie_ctrl register offset within SYSCON > + description: Specifier for configuring PCIe mode and link speed. > > power-domains: > maxItems: 1 > @@ -90,7 +94,7 @@ examples: > <0x00 0x0d000000 0x00 0x00800000>, > <0x00 0x10000000 0x00 0x00001000>; > reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; > - ti,syscon-pcie-ctrl = <&pcie0_ctrl>; > + ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x4070>; > max-link-speed = <3>; > num-lanes = <2>; > power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>; > -- > 2.17.1 >
