Hi Rob, On 5/22/2020 9:24 PM, Rob Herring wrote: > On Thu, May 21, 2020 at 9:37 PM Kishon Vijay Abraham I <kishon@xxxxxx> wrote: >> >> Certain platforms like TI's J721E using Cadence PCIe IP can perform only >> 32-bit accesses for reading or writing to Cadence registers. Convert all >> read and write accesses to 32-bit in Cadence PCIe driver in preparation >> for adding PCIe support in TI's J721E SoC. > > Looking more closely I don't think cdns_pcie_ep_assert_intx is okay > with this and never can be given the PCI_COMMAND and PCI_STATUS > registers are in the same word (IIRC, that's the main reason 32-bit > config space accesses are broken). So this isn't going to work at right, PCI_STATUS has write '1' to clear bits and there's a chance that it could be reset while raising legacy interrupt. While this cannot be avoided for TI's J721E, other platforms doesn't have to have this limitation. > least for EP accesses. And maybe you need a custom .raise_irq() hook > to minimize any problems (such as making the RMW atomic at least from > the endpoint's perspective). This is to make sure EP doesn't update in-consistent state when RC is updating the PCI_STATUS register? Since this involves two different systems, how do we make this atomic? Thanks Kishon
