On Fri, May 8, 2020 at 6:57 PM Drew Fustini <drew@xxxxxxxxxxxxxxx> wrote: > Add gpio-line-names properties to the gpio controller nodes. > BeagleBone boards have P8 and P9 headers [0] which expose many the > AM3358 SoC balls to stacking expansion boards called "capes", or to > other external connections like jumper wires to a breadboard. > > Many of the P8/P9 header pins can muxed to a gpio line. The > gpio-line-names describe which P8/P9 pin that line goes to and the > default mux for that P8/P9 pin. Some lines are not routed to the > P8/P9 headers, but instead are dedicated to some functionality such as > status LEDs. The line name will indicate this. Some line names are > left empty as the corresponding AM3358 balls are not connected. > > The goal is to make it easier for a user viewing the output of gpioinfo > to determine which P8/P9 pin is connected to a line. The output of > gpioinfo on a BeagleBone Black will now look like this: > > gpiochip0 - 32 lines: > line 0: "ethernet" unused input active-high > line 1: "ethernet" unused input active-high Why are the ethernet lines not tagged with respective signal name when right below the SPI lines are explicitly tagged with sclk, cs0 etc? Ethernet is usually RGMII and has signal names like tx_clk, tx_d0, tx_en etc. Also some lines seem to be tagged with the pin number like P9_22, P2_21 below, it seems a bit inconsistent to have much information on some pins and very sketchy information on some. > line 18: "usb" unused input active-high > line 19: "hdmi" unused input active-high Similar comments for these. Yours, Linus Walleij
