> I take it this implies that the LLVM linker does not support the > R_ARM_ALU_PC_Gn relocations? Since otherwise, adrl could simply be > expanded to a pair of adds with the appropriate relocations, letting > the linker fix up the immediates (and the ADD vs SUB bits) Not at the moment. I have a patch in review to add the G0 variants for these in Arm state at reviews.llvm.org/D75349 . As far as I know LLVM MC does not have support for generating the relocations either. This could be added though. I agree that using the G* relocations with a pair of add/sub instructions would be the ideal solution. The adrl psuedo is essentially that but implemented at assembly time. I think it would be possible to implement in LLVM but at the time (4+ years ago) I wasn't confident in finding someone that would think that adrl support was worth the disruption, for example the current Arm assembly backend can only produce 1 instruction as output and adrl requires two. I'd be happy to look at group relocation support in LLD, I haven't got a lot of spare time so progress is likely to be slow though. Peter
