On Thu, Mar 12, 2020 at 09:52:09AM +0530, Lokesh Vutla wrote: > Only the Timer control register(TCLR) cannot be updated when the timer > is running. Registers like Counter register(TCRR), loader register(TLDR), > match register(TMAR) can be updated when the counter is running. Since > TCLR is not updated in pwm_omap_dmtimer_config(), do not stop the > timer for period/duty_cycle update. I'm not sure what is sensible here. Stopping the PWM for a short period is bad, but maybe emitting a wrong period isn't better. You can however optimise it if only one of period or duty_cycle changes. @Thierry, what is your position here? I tend to say a short stop is preferable. > Tested-by: Tony Lindgren <tony@xxxxxxxxxxx> > Signed-off-by: Lokesh Vutla <lokeshvutla@xxxxxx> > --- > drivers/pwm/pwm-omap-dmtimer.c | 21 +++++++-------------- > 1 file changed, 7 insertions(+), 14 deletions(-) > > diff --git a/drivers/pwm/pwm-omap-dmtimer.c b/drivers/pwm/pwm-omap-dmtimer.c > index 85b17b49980b..c56e7256e923 100644 > --- a/drivers/pwm/pwm-omap-dmtimer.c > +++ b/drivers/pwm/pwm-omap-dmtimer.c > @@ -19,6 +19,13 @@ > * Limitations: > * - When PWM is stopped, timer counter gets stopped immediately. This > * doesn't allow the current PWM period to complete and stops abruptly. > + * - When PWM is running and changing both duty cycle and period, > + * we cannot prevent in software that the output might produce > + * a period with mixed settings. Especially when period/duty_cyle > + * is updated while the pwm pin is high, current pwm period/duty_cycle > + * can get updated as below based on the current timer counter: > + * - period for current cycle = current_period + new period > + * - duty_cycle for current period = current period + new duty_cycle. In case we stay with a short stop, adding something like: - The PWM has to be stopped for updates of both period and duty_cycle. Best regards Uwe -- Pengutronix e.K. | Uwe Kleine-König | Industrial Linux Solutions | https://www.pengutronix.de/ |
