Hello Jagadeesh, On Tue, 23 Jun 2009, Pakaravoor, Jagadeesh wrote: > > > + u8 stat2 = 0; > > > + stat2 = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG); > > > + if (stat2 & OMAP_I2C_STAT_BB) > > > + return IRQ_HANDLED; > > > > Why use stat2? Why not just test stat again? > > Stat is read at the beginning of the ISR, what if BB bit gets > cleared/set a while later, not along with RDR, as a corner case? If that is possible, then the comment in this patch needs to be changed: > + /* 3430 I2C Errata 1.15 > + * RDR could be set when the bus is busy, then > + * ignore the interrupt, and clear the bit. > + */ This implies that the state of the BB bit is important when the RDR bit is set. The closest sample we have for that is the contents of the 'stat' variable. > If we keep it this way, re-reading the register; what could be the > potential problem? It doesn't match the definition of the erratum as expressed in the comment. Is it possible for the RDR bit to be erroneously set when BB = 0? - Paul -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
