Hi, The existing divider clock support appears to have an inherent bug because of the bit field width implementation and limitation of divider values based on this. The limitation by bit field only is not enough, as we can have divider settings which accept only certain range of dividers within the full range of the bit-field. Because of this, the divider clock is re-implemented to use min,max,mask values instead of just the bit-field. -Tero -- Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
