* H. Nikolaus Schaller <hns@xxxxxxxxxxxxx> [190904 08:54]: > This adds code and tables to read the silicon revision and > eFuse (speed binned / 720 MHz grade) bits for selecting > opp-v2 table entries. > > Since these bits are not always part of the syscon register > range (like for am33xx, am43, dra7), we add code to directly > read the register values using ioremap() if syscon access fails. This is nice :) Seems to work for me based on a quick test on at least omap36xx. Looks like n900 produces the following though: core: _opp_supported_by_regulators: OPP minuV: 1270000 maxuV: 1270000, not supported by regulator cpu cpu0: _opp_add: OPP not supported by regulators (550000000) But presumably that can be further patched. So for this patch: Acked-by: Tony Lindgren <tony@xxxxxxxxxxx>
