Hi all, > Am 17.08.2019 um 20:47 schrieb André Roth <neolynx@xxxxxxxxx>: > > > Hi Adam, > >> What makes DVFS different from what cpufreq does by changing the >> operating voltage and frequency? > > If I understood correctly, it actively measures and optimizes the > voltages applied by cpufreq since they change with > temperature/manufacturing differences/age. At higher frequencies > (i.e. 1GHz) this is required to not damage the chip or reduce its > lifetime. I also understood that there are some CONTROL_FUSE registers in syscon (e.g. CONTROL_FUSE_OPP1G_VDD1) to specify factory optimized values. Maybe DVFS can/should be added to the ti-cpufreq driver? Interestingly, the n950-n9 device tree simply adds an 1GHz OPP at 1.375V by commit 0f4f1542ea0928f4840d308e411797c0dacac239 https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm/boot/dts/omap3-n950-n9.dtsi?h=v5.3-rc6#n14 This would mean that it would suffice to add the OPP1G to the device tree, at least on the n950. But we have seen some RAM errors on other devices when trying 1GHz. Maybe someone owning and using a mainline kernel on n950 can comment on reliability of this setting. BR, Nikolaus
