Hi Tero, On 8/7/19 8:04 AM, Tero Kristo wrote: > These cause some unwanted timeouts in the kernel, as they depend on > reset and the execution state of the remotecore itself. These details > should be handled by the driver with proper sequencing of events. This can definitely do with some better patch description. What about the changes to the OMAP4 and OMAP5 files? Please see my equivalent downstream patches [1][2][3] for the same though they are using the CLKF_NO_IDLEST flag. regards Suman [1] OMAP4: http://git.ti.com/gitweb/?p=rpmsg/iommu.git;a=commit;h=1979318da6f76809a5e6d652f814b2e80836aa21 [2] OMAP5: http://git.ti.com/gitweb/?p=rpmsg/iommu.git;a=commit;h=69b31b56ceffdec3aed5b0feaa06090f8ee318b6 [3] DRA7: http://git.ti.com/gitweb/?p=rpmsg/iommu.git;a=commit;h=a26129c10cda1d64bec3cd7a03b9acd447df84ea (portions of this patch content are already upstream, the delta being these additional flags). > > Signed-off-by: Tero Kristo <t-kristo@xxxxxx> > --- > drivers/clk/ti/clk-7xx.c | 8 ++++---- > 1 file changed, 4 insertions(+), 4 deletions(-) > > diff --git a/drivers/clk/ti/clk-7xx.c b/drivers/clk/ti/clk-7xx.c > index b57fe09..5208eb8 100644 > --- a/drivers/clk/ti/clk-7xx.c > +++ b/drivers/clk/ti/clk-7xx.c > @@ -25,7 +25,7 @@ > }; > > static const struct omap_clkctrl_reg_data dra7_dsp1_clkctrl_regs[] __initconst = { > - { DRA7_DSP1_MMU0_DSP1_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_dsp_m2_ck" }, > + { DRA7_DSP1_MMU0_DSP1_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_NO_IDLE_POLL, "dpll_dsp_m2_ck" }, > { 0 }, > }; > > @@ -41,7 +41,7 @@ > }; > > static const struct omap_clkctrl_reg_data dra7_ipu1_clkctrl_regs[] __initconst = { > - { DRA7_IPU1_MMU_IPU1_CLKCTRL, dra7_mmu_ipu1_bit_data, CLKF_HW_SUP, "ipu1-clkctrl:0000:24" }, > + { DRA7_IPU1_MMU_IPU1_CLKCTRL, dra7_mmu_ipu1_bit_data, CLKF_HW_SUP | CLKF_NO_IDLE_POLL, "ipu1-clkctrl:0000:24" }, > { 0 }, > }; > > @@ -137,7 +137,7 @@ > }; > > static const struct omap_clkctrl_reg_data dra7_dsp2_clkctrl_regs[] __initconst = { > - { DRA7_DSP2_MMU0_DSP2_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_dsp_m2_ck" }, > + { DRA7_DSP2_MMU0_DSP2_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_NO_IDLE_POLL, "dpll_dsp_m2_ck" }, > { 0 }, > }; > > @@ -164,7 +164,7 @@ > }; > > static const struct omap_clkctrl_reg_data dra7_ipu2_clkctrl_regs[] __initconst = { > - { DRA7_IPU2_MMU_IPU2_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_core_h22x2_ck" }, > + { DRA7_IPU2_MMU_IPU2_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_NO_IDLE_POLL, "dpll_core_h22x2_ck" }, > { 0 }, > }; > >
