On Sun, 7 Jul 2019 22:52:38 -0500, Suman Anna wrote: > The Programmable Real-Time Unit Subsystem (PRUSS) contains an interrupt > controller (INTC) that can handle various system input events and post > interrupts back to the device-level initiators. The INTC can support > upto 64 input events on most SoCs with individual control configuration > and hardware prioritization. These events are mapped onto 10 interrupt > lines through two levels of many-to-one mapping support. Different > interrupt lines are routed to the individual PRU cores or to the > host CPU or to other PRUSS instances. > > The K3 AM65x and J721E SoCs have the next generation of the PRU-ICSS IP, > commonly called ICSSG. The ICSSG interrupt controller on K3 SoCs provide > a higher number of host interrupts (20 vs 10) and can handle an increased > number of input events (160 vs 64) from various SoC interrupt sources. > > Add the bindings document for these interrupt controllers on all the > applicable SoCs. It covers the OMAP architecture SoCs - AM33xx, AM437x > and AM57xx; the Keystone 2 architecture based 66AK2G SoC; the Davinci > architecture based OMAPL138 SoCs, and the K3 architecture based AM65x > and J721E SoCs. > > Signed-off-by: Suman Anna <s-anna@xxxxxx> > Signed-off-by: Andrew F. Davis <afd@xxxxxx> > Signed-off-by: Roger Quadros <rogerq@xxxxxx> > --- > Prior version: https://patchwork.kernel.org/patch/10795771/ > > .../interrupt-controller/ti,pruss-intc.txt | 92 +++++++++++++++++++ > 1 file changed, 92 insertions(+) > create mode 100644 Documentation/devicetree/bindings/interrupt-controller/ti,pruss-intc.txt > Reviewed-by: Rob Herring <robh@xxxxxxxxxx>
