Tony,
On 4/2/19 12:24 PM, Tony Lindgren wrote:
* Dave Gerlach <d-gerlach@xxxxxx> [190402 16:57]:
In certain situations, such as when returning from low power modes, the
EMIF must re-run hardware leveling to properly restore DDR3 access.
This is accomplished by introducing a new ti-emif-sram-pm call,
ti_emif_run_hw_leveling, to check if DDR3 is in use and if so, trigger
the full write and read leveling processes.
OK nice that you also consider devices with LPDDR2 then in case we
start seeing those.
Yes, LPDDR2 will work fine with these. Any thoughts on if this series
should come through you or Santosh?
Regards,
Dave
Regards,
Tony
