Hi, * Suman Anna <s-anna@xxxxxx> [190326 23:22]: > On 3/26/19 6:13 PM, Tony Lindgren wrote: > Hmm, are you envisioning the SYSC reset (OCP SoftReset) here or the PRCM > RSTCTRL hardresets here? The latter in general requires the clocks to be > running first (module won't be in ready status until you deassert the > hardresets with clocks running). You can look up the Warm-reset or > Cold-reset sequences in the TRMs for any of the processors. That's for rstctrl. I just did a quick test with my earlier reset-simple patch and I noticed sgx on am33xx produces a clock error unless we deassert it's rstrctrl before enabling clocks first: gfx-l3-clkctrl:0004:0: failed to enable > I am working on preparing the next version of PRUSS patches with ti-sysc > on AM33xx/AM437x/AM57xx platforms, so will pick up these patches for my > testing. OK great, yes please check and test with your rstctrl use case. I guess you still need to use the reset-simple patch for now until we have a proper prm rstctrl driver. Note that you probably also want to leave out the struct omap_hwmod data from omap_hwmod_*_data.c files with rstctrl entries. Regards, Tony
