The AM3517-EVM uses hsusb1 connected to a USB3320 ULPI Phy
for USB Host. This patch will enable the USB host port in
EHCI mode.
RFC - I am getting Errors:
[ 14.225754] usb 2-1: device descriptor read/64, error -71
[ 15.165746] usb 2-1: device descriptor read/64, error -71
[ 16.095806] usb 2-1: new high-speed USB device number 3 using ehci-omap
[ 16.925760] usb 2-1: device descriptor read/64, error -71
[ 17.865742] usb 2-1: device descriptor read/64, error -71
[ 17.986079] usb usb2-port1: attempt power cycle
[ 19.135783] usb 2-1: new high-speed USB device number 4 using ehci-omap
[ 19.585737] usb 2-1: device not accepting address 4, error -71
[ 20.395752] usb 2-1: new high-speed USB device number 5 using ehci-omap
[ 20.845739] usb 2-1: device not accepting address 5, error -71
[ 20.851958] usb usb2-port1: unable to enumerate USB device
I was hoping someone might have some insight as to why. This doesn't
seem to be any different than any OMAP3 HSUSB1 port and this
method works on a Logic PD DM3730 SOM-LV with the same USB3320 ULPI
Signed-off-by: Adam Ford <aford173@xxxxxxxxx>
diff --git a/arch/arm/boot/dts/am3517-evm.dts b/arch/arm/boot/dts/am3517-evm.dts
index 98aadb0f81c5..135f38e6f6e2 100644
--- a/arch/arm/boot/dts/am3517-evm.dts
+++ b/arch/arm/boot/dts/am3517-evm.dts
@@ -168,6 +168,12 @@
ti,timers = <&timer11>;
#pwm-cells = <3>;
};
+
+ hsusb1_phy: hsusb1_phy {
+ compatible = "usb-nop-xceiv";
+ reset-gpios = <&gpio2 25 GPIO_ACTIVE_LOW>; /* gpio_57 */
+ #phy-cells = <0>;
+ };
};
&davinci_emac {
@@ -228,7 +234,18 @@
status = "disabled";
};
+&usbhshost {
+ /* num-ports = <1>; */
+ port1-mode = "ehci-phy";
+};
+
+&usbhsehci {
+ phys = <&hsusb1_phy>;
+};
+
&omap3_pmx_core {
+ pinctrl-names = "default";
+ pinctrl-0 = <&hsusb1_reset_pins>;
leds_pins: pinmux_leds_pins {
pinctrl-single,pins = <
@@ -287,4 +304,33 @@
OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */
>;
};
+
+ hsusb1_reset_pins: pinmux_hsusb1_reset_pins {
+ pinctrl-single,pins = <
+ OMAP3_CORE1_IOPAD(0x20ba, PIN_OUTPUT | MUX_MODE4) /* gpmc_ncs6.gpio_57 */
+ >;
+ };
+};
+
+&omap3_pmx_core2 {
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&hsusb1_phy_pins>;
+
+ hsusb1_phy_pins: pinmux_hsusb1_phy_pins {
+ pinctrl-single,pins = <
+ OMAP3430_CORE2_IOPAD(0x25d8, PIN_OUTPUT | MUX_MODE3) /* etk_clk.hsusb1_stp */
+ OMAP3430_CORE2_IOPAD(0x25da, PIN_OUTPUT | MUX_MODE3) /* etk_ctl.hsusb1_clk */
+ OMAP3430_CORE2_IOPAD(0x25dc, PIN_INPUT | MUX_MODE3) /* etk_d0.hsusb1_data0 */
+ OMAP3430_CORE2_IOPAD(0x25de, PIN_INPUT | MUX_MODE3) /* etk_d1.hsusb1_data1 */
+ OMAP3430_CORE2_IOPAD(0x25e0, PIN_INPUT | MUX_MODE3) /* etk_d2.hsusb1_data2 */
+ OMAP3430_CORE2_IOPAD(0x25e2, PIN_INPUT | MUX_MODE3) /* etk_d3.hsusb1_data7 */
+ OMAP3430_CORE2_IOPAD(0x25e4, PIN_INPUT | MUX_MODE3) /* etk_d4.hsusb1_data4 */
+ OMAP3430_CORE2_IOPAD(0x25e6, PIN_INPUT | MUX_MODE3) /* etk_d5.hsusb1_data5 */
+ OMAP3430_CORE2_IOPAD(0x25e8, PIN_INPUT | MUX_MODE3) /* etk_d6.hsusb1_data6 */
+ OMAP3430_CORE2_IOPAD(0x25ea, PIN_INPUT | MUX_MODE3) /* etk_d7.hsusb1_data3 */
+ OMAP3430_CORE2_IOPAD(0x25ec, PIN_INPUT | MUX_MODE3) /* etk_d8.hsusb1_dir */
+ OMAP3430_CORE2_IOPAD(0x25ee, PIN_INPUT | MUX_MODE3) /* etk_d9.hsusb1_nxt */
+ >;
+ };
};
--
2.17.0
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