Certain revisions of the TI EMIF IP contain ECC support in them. Reflect
this in the DT binding.
Signed-off-by: Tero Kristo <t-kristo@xxxxxx>
Cc: Tony Lindgren <tony@xxxxxxxxxxx>
Cc: Rob Herring <robh+dt@xxxxxxxxxx>
---
Just resending this patch, missed adding devicetree list on this previously
and it got lost.
.../devicetree/bindings/memory-controllers/ti/emif.txt | 16 +++++++++++++++-
1 file changed, 15 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/memory-controllers/ti/emif.txt b/Documentation/devicetree/bindings/memory-controllers/ti/emif.txt
index 0db6047..f56a347 100644
--- a/Documentation/devicetree/bindings/memory-controllers/ti/emif.txt
+++ b/Documentation/devicetree/bindings/memory-controllers/ti/emif.txt
@@ -3,12 +3,16 @@
EMIF - External Memory Interface - is an SDRAM controller used in
TI SoCs. EMIF supports, based on the IP revision, one or more of
DDR2/DDR3/LPDDR2 protocols. This binding describes a given instance
-of the EMIF IP and memory parts attached to it.
+of the EMIF IP and memory parts attached to it. Certain revisions
+of the EMIF IP controller also contain optional ECC support, which
+corrects one bit errors and detects two bit errors.
Required properties:
- compatible : Should be of the form "ti,emif-<ip-rev>" where <ip-rev>
is the IP revision of the specific EMIF instance.
For am437x should be ti,emif-am4372.
+ For dra7xx should be ti,emif-dra7xx.
+ For k2x family, should be ti,emif-keystone.
- phy-type : <u32> indicating the DDR phy type. Following are the
allowed values
@@ -42,6 +46,10 @@ Optional properties:
- hw-caps-temp-alert : Have this property if the controller
has capability for generating SDRAM temperature alerts
+- interrupts : A list of interrupt specifiers for memory
+ controller interrupts, if available. Required for EMIF instances
+ that support ECC.
+
Example:
emif1: emif@0x4c000000 {
@@ -54,3 +62,9 @@ emif1: emif@0x4c000000 {
hw-caps-ll-interface;
hw-caps-temp-alert;
};
+
+emif1: emif@4c000000 {
+ compatible = "ti,emif-dra7";
+ reg = <0x4c000000 0x200>;
+ interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+};
--
1.9.1
--
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