* Rob Herring <robh@xxxxxxxxxx> [171019 14:07]:
> On Wed, Oct 18, 2017 at 8:02 AM, Benoit Parrot <bparrot@xxxxxx> wrote:
> >> > +Example:
> >> > + vpe {
> >> > + compatible = "ti,vpe";
> >> > + ti,hwmods = "vpe";
> >> > + clocks = <&dpll_core_h23x2_ck>;
> >> > + clock-names = "fck";
> >> > + reg = <0x489d0000 0x120>,
> >> > + <0x489d0300 0x20>,
> >> > + <0x489d0400 0x20>,
> >> > + <0x489d0500 0x20>,
> >> > + <0x489d0600 0x3c>,
> >> > + <0x489d0700 0x80>,
> >>
> >> Is there other stuff between these regions?
> >
> > No, they listed separately because each sub-region/module is
> > individually mapped and accessed using a starting 0 offset.
>
> So you are going to use 48KB of virtual memory to map 2KB of
> registers? Because each ioremap uses 8KB (1 page plus 1 guard page)
> last time i looked (which has been a while).
>
> But it's your platform.
We should have cached regions for all interconnects so this should
not be a problem. Worth checking that the areas are listed in
dra7xx_io_desc[] and for other SoCs too to avoid this issue.
Regards,
Tony
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