* Russell King - ARM Linux <linux@xxxxxxxxxxxxxxx> [170525 10:00]: > On Thu, May 25, 2017 at 09:15:19AM -0700, Florian Fainelli wrote: > > On 05/18/2017 03:52 AM, Russell King - ARM Linux wrote: > > > As a result of a recent bug report, it has been found that certain CPUs > > > must always have SMP mode enabled in order for the caches to work. > > > > > > Remove the conditional on setting the SMP bit(s). > > > > > > Signed-off-by: Russell King <rmk+kernel@xxxxxxxxxxxxxxx> > > > --- > > > This needs to be tested on: > > > > > > - Cortex A5MP > > > - Cortex A9MP > > > - Cortex R7MP > > > - Cortex A7MP > > > - Cortex A12MP > > > - Cortex A15MP > > > - Cortex A17MP > > > - Brahma B15 > > > > Sorry just saw this, what kind of test do you want me to run on B15? > > Should I build a !SMP kernel, or force a SMP kernel with maxcpus=1? > > What I'm after is testing on any single-core systems with these SMP > capable cores. If the core never appears in a single-core configuration, > then please let me know so it can be crossed off the list. > > With the bug that crept in fixed (as pointed out by Tony) there is no > difference for kernels built with SMP enabled and detected as a SMP > capable CPU. At least am437x needs to be tested as it's UP with some quirks. Regards, Tony -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
