Re: [PATCH v2 0/2] PM: OMAP3 SDRC: fix some SDRAM settings for Qimonda parts

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* Paul Walmsley <paul@xxxxxxxxx> [090514 12:52]:
> Hi,
> 
> This series updates some SDRAM parameter settings for the Qimonda parts
> used on some 3430SDP boards.
> 
> Drop the 133.3MHz/66.6MHz rates from the Qimonda SDRAM file - these were only
> used on some early Labrador boards with slower SDRAM parts.  Thanks to
> Richard Woodruff <r-woodruff2@xxxxxx> for help with this patch.
> 
> Finally some 3430SDP boards are using bootloaders with rounded DPLL3 rates
> (e.g., 166000000 Hz rather than 165941176 Hz); update the Qimonda SDRAM
> parameters.  This resolves -EINVALs during boot-time "Reprogramming SDRC"
> on 3430SDPs with updated bootloaders.  Thanks to Kevin Hilman
> <khilman@xxxxxxxxxxxxxxxxxxx> for reporting this issue and testing
> the patch.
> 
> These patches will be queued up into the omap-clock-testing branch at the
> next opportunity.

I've merged these two patches already into your older sdram patches
in the omap3-upstream queue.

Tony
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