On Tue, 18 Apr 2017 12:06:40 +0300 Jyri Sarha <jsarha@xxxxxx> wrote: > On 04/15/17 10:44, Andreas Kemnade wrote: > > Hi Jyri, > > > > I am often seeing only some moving horizontal white strips (maybe 1-2 > > pixels thick) when I boot my gta04 (omap 3 dm3730 + panel_tpo_td028ttec1 > > + encoder_opa362). > > > > After a git bisect session, the verdict is: this patch is guilthy: > > > > It is weird how committing the same configuration in different order has > this effect. I have a feeling that this change has some how triggered > another bug that has been hidden until now. > > Sync lost error (the bit 14 of DISPC_IRQSTS) is usually indication of > some misconfiguration of the HW. > > Could you provide us with the register dumps of the error situation, > by copying them from /sys/kernel/debug/omapdss/* (or where ever you have > the debugfs mounted). > The diff between ok and not ok: --- nok 2017-04-19 23:19:40.474940077 +0200 +++ ok 2017-04-19 23:13:58.077690744 +0200 @@ -10,12 +10,12 @@ DISPC_REVISION 00000030 DISPC_SYSCONFIG 00002015 DISPC_SYSSTATUS 00000001 -DISPC_IRQSTATUS 00000002 +DISPC_IRQSTATUS 000100a2 DISPC_IRQENABLE 0000d640 DISPC_CONTROL 00018309 DISPC_CONFIG 00000204 DISPC_CAPABLE 000003ff -DISPC_LINE_STATUS 00000000 +DISPC_LINE_STATUS 00000117 DISPC_LINE_NUMBER 00000000 DISPC_GLOBAL_ALPHA 000000ff DISPC_DEFAULT_COLOR(LCD) 00000000 The full list of nok: - DSS - FCK = 66461539 - DISPC - dispc fclk source = FCK fck 66461539 - LCD - LCD clk source = FCK lck 22153846 lck div 3 pck 22153846 pck div 1 DISPC_REVISION 00000030 DISPC_SYSCONFIG 00002015 DISPC_SYSSTATUS 00000001 DISPC_IRQSTATUS 00000002 DISPC_IRQENABLE 0000d640 DISPC_CONTROL 00018309 DISPC_CONFIG 00000204 DISPC_CAPABLE 000003ff DISPC_LINE_STATUS 00000000 DISPC_LINE_NUMBER 00000000 DISPC_GLOBAL_ALPHA 000000ff DISPC_DEFAULT_COLOR(LCD) 00000000 DISPC_TRANS_COLOR(LCD) 00000000 DISPC_SIZE_MGR(LCD) 027f01df DISPC_TIMING_H(LCD) 00701707 DISPC_TIMING_V(LCD) 00200401 DISPC_POL_FREQ(LCD) 00023000 DISPC_DIVISORo(LCD) 00030001 DISPC_DATA_CYCLE1(LCD) 00000000 DISPC_DATA_CYCLE2(LCD) 00000000 DISPC_DATA_CYCLE3(LCD) 00000000 DISPC_CPR_COEF_R(LCD) 00000000 DISPC_CPR_COEF_G(LCD) 00000000 DISPC_CPR_COEF_B(LCD) 00000000 DISPC_DEFAULT_COLOR(TV) 00000000 DISPC_TRANS_COLOR(TV) 00000000 DISPC_SIZE_MGR(TV) 00000000 DISPC_OVL_BA0(GFX) be900000 DISPC_OVL_BA1(GFX) be900000 DISPC_OVL_POSITION(GFX) 00000000 DISPC_OVL_SIZE(GFX) 027f01df DISPC_OVL_ATTRIBUTES(GFX) 00000091 DISPC_OVL_FIFO_THRESHOLD(GFX) 03ff03c0 DISPC_OVL_FIFO_SIZE_STATUS(GFX) 00000400 DISPC_OVL_ROW_INC(GFX) 00000001 DISPC_OVL_PIXEL_INC(GFX) 00000001 DISPC_OVL_PRELOAD(GFX) 00000100 DISPC_OVL_WINDOW_SKIP(GFX) 00000000 DISPC_OVL_TABLE_BA(GFX) 00000000 DISPC_OVL_BA0(VID1) 00000000 DISPC_OVL_BA1(VID1) 00000000 DISPC_OVL_POSITION(VID1) 00000000 DISPC_OVL_SIZE(VID1) 00000000 DISPC_OVL_ATTRIBUTES(VID1) 00008000 DISPC_OVL_FIFO_THRESHOLD(VID1) 03ff03c0 DISPC_OVL_FIFO_SIZE_STATUS(VID1) 00000400 DISPC_OVL_ROW_INC(VID1) 00000001 DISPC_OVL_PIXEL_INC(VID1) 00000001 DISPC_OVL_PRELOAD(VID1) 00000100 DISPC_OVL_FIR(VID1) 00000000 DISPC_OVL_PICTURE_SIZE(VID1) 00000000 DISPC_OVL_ACCU0(VID1) 00000000 DISPC_OVL_ACCU1(VID1) 00000000 DISPC_OVL_BA0(VID2) 00000000 DISPC_OVL_BA1(VID2) 00000000 DISPC_OVL_POSITION(VID2) 00000000 DISPC_OVL_SIZE(VID2) 00000000 DISPC_OVL_ATTRIBUTES(VID2) 00008000 DISPC_OVL_FIFO_THRESHOLD(VID2) 03ff03c0 DISPC_OVL_FIFO_SIZE_STATUS(VID2) 00000400 DISPC_OVL_ROW_INC(VID2) 00000001 DISPC_OVL_PIXEL_INC(VID2) 00000001 DISPC_OVL_PRELOAD(VID2) 00000100 DISPC_OVL_FIR(VID2) 00000000 DISPC_OVL_PICTURE_SIZE(VID2) 00000000 DISPC_OVL_ACCU0(VID2) 00000000 DISPC_OVL_ACCU1(VID2) 00000000 DISPC_OVL_FIR_COEF_H_0(VID1) 00000000 DISPC_OVL_FIR_COEF_H_1(VID1) 00000000 DISPC_OVL_FIR_COEF_H_2(VID1) 00000000 DISPC_OVL_FIR_COEF_H_3(VID1) 00000000 DISPC_OVL_FIR_COEF_H_4(VID1) 00000000 DISPC_OVL_FIR_COEF_H_5(VID1) 00000000 DISPC_OVL_FIR_COEF_H_6(VID1) 00000000 DISPC_OVL_FIR_COEF_H_7(VID1) 00000000 DISPC_OVL_FIR_COEF_HV_0(VID1) 00000000 DISPC_OVL_FIR_COEF_HV_1(VID1) 00000000 DISPC_OVL_FIR_COEF_HV_2(VID1) 00000000 DISPC_OVL_FIR_COEF_HV_3(VID1) 00000000 DISPC_OVL_FIR_COEF_HV_4(VID1) 00000000 DISPC_OVL_FIR_COEF_HV_5(VID1) 00000000 DISPC_OVL_FIR_COEF_HV_6(VID1) 00000000 DISPC_OVL_FIR_COEF_HV_7(VID1) 00000000 DISPC_OVL_CONV_COEF_0(VID1) 0199012a DISPC_OVL_CONV_COEF_1(VID1) 012a0000 DISPC_OVL_CONV_COEF_2(VID1) 079c0730 DISPC_OVL_CONV_COEF_3(VID1) 0000012a DISPC_OVL_CONV_COEF_4(VID1) 00000205 DISPC_OVL_FIR_COEF_V_0(VID1) 00000000 DISPC_OVL_FIR_COEF_V_1(VID1) 00000000 DISPC_OVL_FIR_COEF_V_2(VID1) 00000000 DISPC_OVL_FIR_COEF_V_3(VID1) 00000000 DISPC_OVL_FIR_COEF_V_4(VID1) 00000000 DISPC_OVL_FIR_COEF_V_5(VID1) 00000000 DISPC_OVL_FIR_COEF_V_6(VID1) 00000000 DISPC_OVL_FIR_COEF_V_7(VID1) 00000000 DISPC_OVL_FIR_COEF_H_0(VID2) 00000000 DISPC_OVL_FIR_COEF_H_1(VID2) 00000000 DISPC_OVL_FIR_COEF_H_2(VID2) 00000000 DISPC_OVL_FIR_COEF_H_3(VID2) 00000000 DISPC_OVL_FIR_COEF_H_4(VID2) 00000000 DISPC_OVL_FIR_COEF_H_5(VID2) 00000000 DISPC_OVL_FIR_COEF_H_6(VID2) 00000000 DISPC_OVL_FIR_COEF_H_7(VID2) 00000000 DISPC_OVL_FIR_COEF_HV_0(VID2) 00000000 DISPC_OVL_FIR_COEF_HV_1(VID2) 00000000 DISPC_OVL_FIR_COEF_HV_2(VID2) 00000000 DISPC_OVL_FIR_COEF_HV_3(VID2) 00000000 DISPC_OVL_FIR_COEF_HV_4(VID2) 00000000 DISPC_OVL_FIR_COEF_HV_5(VID2) 00000000 DISPC_OVL_FIR_COEF_HV_6(VID2) 00000000 DISPC_OVL_FIR_COEF_HV_7(VID2) 00000000 DISPC_OVL_CONV_COEF_0(VID2) 0199012a DISPC_OVL_CONV_COEF_1(VID2) 012a0000 DISPC_OVL_CONV_COEF_2(VID2) 079c0730 DISPC_OVL_CONV_COEF_3(VID2) 0000012a DISPC_OVL_CONV_COEF_4(VID2) 00000205 DISPC_OVL_FIR_COEF_V_0(VID2) 00000000 DISPC_OVL_FIR_COEF_V_1(VID2) 00000000 DISPC_OVL_FIR_COEF_V_2(VID2) 00000000 DISPC_OVL_FIR_COEF_V_3(VID2) 00000000 DISPC_OVL_FIR_COEF_V_4(VID2) 00000000 DISPC_OVL_FIR_COEF_V_5(VID2) 00000000 DISPC_OVL_FIR_COEF_V_6(VID2) 00000000 DISPC_OVL_FIR_COEF_V_7(VID2) 00000000 DSS_REVISION 00000020 DSS_SYSCONFIG 00000001 DSS_SYSSTATUS 00000001 DSS_CONTROL 00000018 VENC_F_CONTROL 00000087 VENC_VIDOUT_CTRL 00000000 VENC_SYNC_CTRL 00008000 VENC_LLEN 00000359 VENC_FLENS 0000020c VENC_HFLTR_CTRL 00000000 VENC_CC_CARR_WSS_CARR 043f2631 VENC_C_PHASE 00000000 VENC_GAIN_U 00000102 VENC_GAIN_V 0000016c VENC_GAIN_Y 0000012f VENC_BLACK_LEVEL 00000043 VENC_BLANK_LEVEL 00000038 VENC_X_COLOR 00000000 VENC_M_CONTROL 00000001 VENC_BSTAMP_WSS_DATA 00000038 VENC_S_CARR 21f07c1f VENC_LINE21 00000000 VENC_LN_SEL 010b0015 VENC_L21__WC_CTL 00001400 VENC_HTRIGGER_VTRIGGER 00000000 VENC_SAVID__EAVID 069300f4 VENC_FLEN__FAL 0016020c VENC_LAL__PHASE_RESET 00060107 VENC_HS_INT_START_STOP_X 007e034e VENC_HS_EXT_START_STOP_X 000f0359 VENC_VS_INT_START_X 01a00000 VENC_VS_INT_STOP_X__VS_INT_START_Y 020901a0 VENC_VS_INT_STOP_Y__VS_EXT_START_X 01ac0022 VENC_VS_EXT_STOP_X__VS_EXT_START_Y 020d01ac VENC_VS_EXT_STOP_Y 00000006 VENC_AVID_START_STOP_X 03480078 VENC_AVID_START_STOP_Y 02060026 VENC_FID_INT_START_X__FID_INT_START_Y 0001008a VENC_FID_INT_OFFSET_Y__FID_EXT_START_X 01ac0106 VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y 01060006 VENC_TVDETGP_INT_START_STOP_X 00140001 VENC_TVDETGP_INT_START_STOP_Y 00010001 VENC_GEN_CTRL 00ff0000 VENC_OUTPUT_CONTROL 00000008 VENC_OUTPUT_TEST 00000000 Regards, Andreas
Attachment:
pgpmFF8a9lQUH.pgp
Description: OpenPGP digital signature
