* Charles Keepax <ckeepax@xxxxxxxxxxxxxxxxxxxxxxxxxxx> [170320 08:15]: > On Thu, Mar 16, 2017 at 05:36:30PM -0700, Tony Lindgren wrote: > > At least Motorola CPCAP PMIC needs it's device interrupts re-read > > until there are no more interrupts. Otherwise the PMIC interrupt to > > the SoC will eventually stop toggling. > > > > Let's allow doing that by introducing a flag for handle_reread > > and by splitting regmap_irq_thread() into two separate functions > > for regmap_read_irq_status() and regmap_irq_handle_pending(). > > > > Is this actually a property of this hardware or is this just a > result of connecting a device that generates level IRQs to a host > that is expecting an edge triggered IRQ? Well the CPCAP PMIC interrupt is connected to a GPIO edge interrupt on the SoC in the Motorola v3.8 based kernel tree. But what the CPCAP PMIC interrupt handler does in the Motorola kernel is keep handling the CPCAP internal interrupts (and also keep reading the SoC GPIO line status!) until the GPIO line changes status. So yeah it's a property of the CPCAP PMIC hardware. Changing the GPIO interrupt to level makes no difference here. It's not clear why they had marked the CPCAP PMIC to SoC GPIO interrupt as edge though in the Motorola kernel. My guess is that some PMIC to SoC wake-up events are edge interrupts. So we have it set up as edge interrupt in the mainline kernel too. Regards, Tony -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
