Hi, >-----Original Message----- >From: Hugo Vincent >Sent: 11 May, 2009 05:15 > >It seems that the TWL4030_MADC_BUSY bit gets set and never >cleared (as in the aforementioned nabble thread). > >Any ideas? I believe Overo board has sysclk other than 26MHz. Please check GPBR1 register settings for MADC_HFCLK_EN and DEFAULT_MADC_CLK_EN bits. Those bits should be configured *before* sysclk is set in CFG_BOOT. -- Regards, Mikko-- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
