> I managed to find the register to read the max speed in the DM3730 TRM
> (it's not listed in the 3630 version). On a DM3730, If we read address
> 0x4800244C and bit 9 is set, it is a 1 GHz processor, otherwise it's
> 800 MHz. I don't know if the 3630 is the same, but maybe someone from
> TI can confirm or someone in the community with a 3630 board.
>
> In my head I was thinking that when calculating the frequency ceiling,
> we'd compare it to a value based on bit 9 if the CPU family was a
> 36xx/37xx. If something was already done, I can copy that concept
> instead.
I was looking at this in some other context recently for 3630.
CONTROL_FEATURE_OMAP_STATUS is at 0x4800244C. Bit9 is defined as the SPEED_BINNED bit.
IIRC, its purpose was as you intuit. I would be surprised if an old patch does not exist in mail group archives.
For 1GHZ, along with probing VDD, you should probe U4:cap_vdd_bb_mpu_iva on U4 to see if FBB is engaged, the cap should read 1V, if its .4 it is in bypass, or worse in RBB. FBB is needed to ensure 1GHz is stable at DM voltage across devices.
Regards,
Richard W.
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