Hi,
Tony Lindgren <tony@xxxxxxxxxxx> writes:
>> Is there also some dwc3 internal clock? If we assume the usb_otg_ss
>> module is properly enabled it could be some dwc3 internal clock not
>> enabled?
>>
>> We do have a srst_udelay needed for enabling musb controller for some
>> SoCs, I'll check if that's the case here.
>
> If there are no dwc3 internal clocks that may be causing the imprecise
> external abort, then most likely we should apply the following change
> for srst_udelay. Looks like srst_udelay value of 2 is not enough here
> but 3 seems to do the job.
>
> The issue of the spurious interrupts on dwc3 probe remains though.
>
> Regards,
>
> Tony
>
> 8< ------------------------------------
> --- a/arch/arm/mach-omap2/omap_hwmod_54xx_data.c
> +++ b/arch/arm/mach-omap2/omap_hwmod_54xx_data.c
> @@ -1952,6 +1952,7 @@ static struct omap_hwmod omap54xx_usb_tll_hs_hwmod = {
> static struct omap_hwmod_class_sysconfig omap54xx_usb_otg_ss_sysc = {
> .rev_offs = 0x0000,
> .sysc_offs = 0x0010,
> + .srst_udelay = 3,
nothing against it. Would be nice if TI could confirm this is needed and
check if other families might also need it.
--
balbi
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