* Tony Lindgren <tony@xxxxxxxxxxx> [160418 17:15]: > * Tony Lindgren <tony@xxxxxxxxxxx> [160418 16:34]: > > * Grygorii Strashko <grygorii.strashko@xxxxxx> [160418 10:44]: > > > The Davinci MDIO hwod perform only one function now - registers "fck" > > > clock alias for MDIO functional clock. From all other points of view > > > it's fake: it's part of cpsw and do not have clkctrl or sysc > > > registers. > > > > > > Hence, its safe to remove it now, because "fck" clock is added > > > in DT for Davinci MDIO node explicitly. > > > > I think you're right here. At least dra7 has just a single module > > for cpsw at 0x48484000, ap 3 10.0, size 0x4000. I'll check the > > other SoCs too. > > Yeah it seems we only have one module for all the cpsw related > IP blocks. So are these safe to apply in whatever order? Regards, Tony -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
