On 11/30, Tero Kristo wrote: > Errata i810 states that DPLL controller can get stuck while transitioning > to a power saving state, while its M/N ratio is being re-programmed. > > As a workaround, before re-programming the M/N ratio, SW has to ensure > the DPLL cannot start an idle state transition. SW can disable DPLL > idling by setting the DPLL AUTO_DPLL_MODE=0 or keeping a clock request > active by setting a dependent clock domain in SW_WKUP. > > This errata impacts OMAP5 and DRA7 chips, so enable the errata for these. > > Signed-off-by: Tero Kristo <t-kristo@xxxxxx> > --- Acked-by: Stephen Boyd <sboyd@xxxxxxxxxxxxxx> -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
