Hi, On Sun, Apr 05, 2015 at 06:13:47AM +0200, Matthijs van Duin wrote: > On 4 April 2015 at 00:52, Tony Lindgren <tony@xxxxxxxxxxx> wrote: > > Right, it affects n900 for sure. My point is that it also seems to > > affect 37xx versions not listed to suffer from this issue. > > They shouldn't... erratum 430973 only affected Cortex-A8 r1, and the > dm37xx should have an r3p2 right? > > A word of caution though: at least on the DM814x and AM335x, secure > ROM sets bit 6 (IBE) in the Auxiliary Control Register, thereby > enabling BTB invalidate instructions (which normally execute as nops). > This is presumably a leftover of the erratum 430973 workaround, but it > means there is a risk of running afoul of erratum 687067 if BTB > invalidate by MVA instructions are actually used. > > I would actually suggest clearing IBE if it set on Cortex-A8 r2 or > later processors and a secure monitor call is available to do so > (there is on the DM814x and AM335x, dunno about the 37xx), also for > performance reasons: BTB invalidates are quite expensive instructions > (when enabled). So if I understand the issue correct, it would be ok to enable the 430973 workaround in cpu_v7_switch_mm for arm multiplatform kernels (mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB). On unaffected Cortex-A8 platforms the IBE bit should be unset (resulting in a nop instead of the BTB flush). So assuming, that the same is true for non Cortex-A8 platforms: Can the workaround simply be enabled by default if CPU_V7 is selected? -- Sebastian
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