Hi Mike, On Wed, Sep 03, 2014 at 12:22:03PM -0700, Mike Turquette wrote: > Quoting Tero Kristo (2014-08-21 06:47:45) > > In some cases, clocks can switch their parent with clk_set_rate, for > > example clk_mux can do this in some cases. Current implementation of > > clk_change_rate uses un-safe list iteration on the clock children, which > > will cause wrong clocks to be parsed in case any of the clock children > > change their parents during the change rate operation. Fixed by using > > the safe list iterator instead. > > > > The problem was detected due to some divide by zero errors generated > > by clock init on dra7-evm board, see discussion under > > http://article.gmane.org/gmane.linux.ports.arm.kernel/349180 for details. > > > > Signed-off-by: Tero Kristo <t-kristo@xxxxxx> > > To: Mike Turquette <mturquette@xxxxxxxxxx> > > Reported-by: Nishanth Menon <nm@xxxxxx> > > Applied to clk-fixes. v3.17-rc5 and today's next still exhibit the same bug. Any chance we can this fix into v3.17-final ? -- balbi
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