On Tue, Aug 26, 2014 at 04:17:58PM +0200, Tomasz Figa wrote:
> Exynos4 SoCs equipped with an L2C-310 cache controller and running under
> secure firmware require certain registers of aforementioned IP to be
> accessed only from secure mode. This means that SMC calls are required
> for certain register writes. To handle this, an implementation of
> .write_sec and .configure callbacks is provided by this patch.
>
> Signed-off-by: Tomasz Figa <t.figa@xxxxxxxxxxx>
> ---
> arch/arm/mach-exynos/firmware.c | 38 ++++++++++++++++++++++++++++++++++++++
> 1 file changed, 38 insertions(+)
>
> diff --git a/arch/arm/mach-exynos/firmware.c b/arch/arm/mach-exynos/firmware.c
> index f5e626d..554b350 100644
> --- a/arch/arm/mach-exynos/firmware.c
> +++ b/arch/arm/mach-exynos/firmware.c
> @@ -17,6 +17,7 @@
> #include <asm/cacheflush.h>
> #include <asm/cputype.h>
> #include <asm/firmware.h>
> +#include <asm/hardware/cache-l2x0.h>
> #include <asm/suspend.h>
>
> #include <mach/map.h>
> @@ -120,6 +121,31 @@ static const struct firmware_ops exynos_firmware_ops = {
> .resume = exynos_resume,
> };
>
> +static void exynos_l2_write_sec(unsigned long val, unsigned reg)
> +{
> + switch (reg) {
> + case L2X0_CTRL:
> + if (val & L2X0_CTRL_EN)
> + exynos_smc(SMC_CMD_L2X0INVALL, 0, 0, 0);
If we're calling this with the cache already enabled, presumably you're
doing this to cover the case where we're disabling the cache.
1. Do you really want to *invalidate* the L2 cache, discarding its
contents?
2. Don't you think that... if you needed something like this here, then
it could be a defficiency in the common code?
If (2) doesn't apply, then should be a comment here why this is needed.
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according to speedtest.net.
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