On Fri, Sep 12, 2014 at 11:32:25AM -0700, Tony Lindgren wrote: > On some ARMs at least the memory can be mapped pgprot_noncached() > and still be working for atomic operations. As pointed out by > Colin Cross <ccross@xxxxxxxxxxx>, in some cases you do want to use > pgprot_noncached() if the SoC supports it to see a debug printk > just before a write hanging the system. > > On ARMs, the atomic operations on strongly ordered memory are > implementation defined. So let's provide an optional kernel parameter > for configuring noncached memory, and use pgprot_writecombine() by > default. Can we clean up this terminology please? Writecombine memory is not cached - write combine memory bypasses the caches entirely. What it doesn't bypass are store buffers, which may combine two writes together. So, calling it "cached" is misleading. Secondly, memory returned by ioremap() is not strongly ordered, it is device memory. There's three main classifications of memory on ARM: strongly ordered, device and normal memory. Normal memory has attributes which define whether it is write combining, or cacheable in some way (and if so, how it's cacheable.) Exclusives are always permitted to normal memory. The other two are implementation defined. While an implementation may offer it on strongly ordered, that doesn't mean that it also supports it on device memory. Lastly, aliased mappings are something that ARM has always strongly discouraged on ARMv6+ (it was plain down-right unpredictable, but it's now "strongly discouraged") and remapping memory with different memory type should be avoided. -- FTTC broadband for 0.8mile line: currently at 9.5Mbps down 400kbps up according to speedtest.net. -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
