On 09/09/2014 04:55 PM, Roger Quadros wrote:
> The SoC supports 2 DCAN nodes. Add them.
I think you should put the device-tree ml for DT related patches on Cc.
>
> Signed-off-by: Roger Quadros <rogerq@xxxxxx>
> ---
> arch/arm/boot/dts/dra7.dtsi | 30 ++++++++++++++++++++++++++++++
> 1 file changed, 30 insertions(+)
>
> diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
> index 370009e..09d5739 100644
> --- a/arch/arm/boot/dts/dra7.dtsi
> +++ b/arch/arm/boot/dts/dra7.dtsi
> @@ -34,6 +34,8 @@
> serial3 = &uart4;
> serial4 = &uart5;
> serial5 = &uart6;
> + d_can0 = &dcan1;
> + d_can1 = &dcan2;
> };
>
> timer {
> @@ -1267,6 +1269,34 @@
> ti,irqs-skip = <10 133 139 140>;
> ti,irqs-safe-map = <0>;
> };
> +
> + dcan1: can@481cc000 {
> + compatible = "bosch,d_can";
> + ti,hwmods = "dcan1";
> + reg = <0x4ae3c000 0x2000>,
> + <0x558 0x4>; /* index to RAMINIT reg within syscon */
Putting the offset within the syscon here doesn't look good.
> + ti,raminit-syscon = <&dra7_ctrl_core>;
Why not add it as a second parameter to the ti,raminit-syscon instead?
> + ti,raminit-start-bit = <3>;
> + ti,raminit-done-bit = <1>;
> + ti,raminit-pulse;
> + interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&dcan1_sys_clk_mux>;
> + status = "disabled";
> + };
> +
> + dcan2: can@481d0000 {
> + compatible = "bosch,d_can";
> + ti,hwmods = "dcan2";
> + reg = <0x48480000 0x2000>,
> + <0x558 0x4>; /* index to RAMINIT reg within syscon */
> + ti,raminit-syscon = <&dra7_ctrl_core>;
> + ti,raminit-start-bit = <5>;
> + ti,raminit-done-bit = <2>;
> + ti,raminit-pulse;
> + interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&sys_clkin1>;
> + status = "disabled";
> + };
> };
> };
>
>
Marc
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