On 05/06/2014 04:39 PM, Peter Ujfalusi wrote:
>>> Tero: can I have your ack for this patch or do you have further concerns?
>>
>> Yea looks good to me, except for the fact that there is some work on getting
>> default rate/parent support through DT. I would like a comment from Mike about
>> the estimate when this can get in, and whether we should merge intermediate
>> solutions still like this.
>>
>> Anyway, you can consider this patch acked by me, I'll let Mike to decide what
>> to do with it though.
>
> Do you have anything against this patch? Since right now there is no other
> ways to fix the ABE DPLL for dra7 it would be great if we could have this in
> till we have the final solution. Also I'd like to point out that the original
> frequency the ABE DPLL was not correct and renders the audio to be not usable
> on the platform.
Mike: can we have this patch still pushed for 3.16? I can resend it right away
if you lost the original patch.
Thanks,
Péter
>
>>>>
>>>>>
>>>>> -Tero
>>>>>
>>>>>>
>>>>>> Signed-off-by: Peter Ujfalusi <peter.ujfalusi@xxxxxx>
>>>>>> ---
>>>>>> drivers/clk/ti/clk-7xx.c | 7 ++++++-
>>>>>> 1 file changed, 6 insertions(+), 1 deletion(-)
>>>>>>
>>>>>> diff --git a/drivers/clk/ti/clk-7xx.c b/drivers/clk/ti/clk-7xx.c
>>>>>> index f7e40734c819..19a55bf407dd 100644
>>>>>> --- a/drivers/clk/ti/clk-7xx.c
>>>>>> +++ b/drivers/clk/ti/clk-7xx.c
>>>>>> @@ -16,7 +16,7 @@
>>>>>> #include <linux/clkdev.h>
>>>>>> #include <linux/clk/ti.h>
>>>>>>
>>>>>> -#define DRA7_DPLL_ABE_DEFFREQ 361267200
>>>>>> +#define DRA7_DPLL_ABE_DEFFREQ 180633600
>>>>>> #define DRA7_DPLL_GMAC_DEFFREQ 1000000000
>>>>>>
>>>>>>
>>>>>> @@ -322,6 +322,11 @@ int __init dra7xx_dt_clk_init(void)
>>>>>> if (rc)
>>>>>> pr_err("%s: failed to configure ABE DPLL!\n", __func__);
>>>>>>
>>>>>> + dpll_ck = clk_get_sys(NULL, "dpll_abe_m2x2_ck");
>>>>>> + rc = clk_set_rate(dpll_ck, DRA7_DPLL_ABE_DEFFREQ * 2);
>>>>>> + if (rc)
>>>>>> + pr_err("%s: failed to configure ABE DPLL m2x2!\n", __func__);
>>>>>> +
>>>>>> dpll_ck = clk_get_sys(NULL, "dpll_gmac_ck");
>>>>>> rc = clk_set_rate(dpll_ck, DRA7_DPLL_GMAC_DEFFREQ);
>>>>>> if (rc)
>>>>>>
>>>>>
>>>>
>>>>
>>>
>>
>
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