>From: Guido Martínez [mailto:guido@xxxxxxxxxxxxxxxxxxxx] >>On Tue, Jun 24, 2014 at 05:54:24PM +0530, Pekon Gupta wrote: [...] >> +&gpmc { >> + ranges = <0 0 0 0x01000000>; /* address range = 16MB (minimum GPMC partition) */ >> + nand@0,0 { >> + status = "disabled"; >> + reg = <0 0 4>; /* device IO registers */ >> + pinctrl-names = "default"; >> + pinctrl-0 = <&bbcape_nand_flash_pins>; >This doesn't seem to work as pinctrl properties are not parsed for >childs of the gpmc node. Did this work for you? >Putting this in the gpmc node makes it work, but how will we control >pins for the nand and nor independently? I believe there is currently no >support for muxing individual gpmc devices. If we want to add both >devices to the DT and enable them as needed we'd need to add support for >this, right? > Yes, And that should be the case, because different devices would be connected to different chip-selects, so there should be support of providing individual pin-mux for different GPMC devices. Currently both NAND and NOR cape share GPMC_CS0, so both NAND and NOR capes will not work simultaneously. But I'm planning to modify NOR cape hardware at my end to use GPMC_CS1 instead of GPMC_CS0. - NAND on GPMC_CS0 - NOR on GPMC_CS1 In addition to pin-mux you may also require following patch: http://www.spinics.net/lists/linux-omap/msg107950.html Also, I should have marked this series as RFC as its not fully tested. My main intention was to get acknowledgement about cape DTS from various users and Tony Lindgren <tony@xxxxxxxxxxx>. Now as Tony has given some acceptance for these kind of cape DTS, I'll clean-up and re-send these patches with better testing and GPMC fixes. with regards, pekon with regards, pekon -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
