The DESHDCP clock is required only by the DES-HDCP block within HDMI in DSS. However, if the clock isn't set before DSS clock domian is enabled, the clock domain never comes out of idle state. This is because the DSS IP is designed in such a way that if DES-HDCP block can't transition from idle state, the entire DSS clock domain also cannot transition from idle to enabled. DES-HDCP block needs the DESHDCP clock enabled to transition from idle successfully. We enable the deshdcp clock in dra7xx_clk_init() which happens before omap hwmods are setup. This clock is effectively a gate clock with the parent as DSS_L3_GICLK. The parent is an automatically controlled clock by DSS clock domain and hence doesn't have a clock node associated to it. Since DSS_L3_GICLK is derived from the OCP clock, we set the dss_deshdcp_clk's parent as l3_iclk_div. Leaving this bit enabled doesn't prevent DSS or the system to suspend, and only a very few flops get this clock all the time. So there is negligible impact. Signed-off-by: Archit Taneja <archit@xxxxxx> --- drivers/clk/ti/clk-7xx.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/clk/ti/clk-7xx.c b/drivers/clk/ti/clk-7xx.c index f7e4073..3f73a02 100644 --- a/drivers/clk/ti/clk-7xx.c +++ b/drivers/clk/ti/clk-7xx.c @@ -179,6 +179,7 @@ static struct ti_dt_clk dra7xx_clks[] = { DT_CLK(NULL, "dss_hdmi_clk", "dss_hdmi_clk"), DT_CLK(NULL, "dss_video1_clk", "dss_video1_clk"), DT_CLK(NULL, "dss_video2_clk", "dss_video2_clk"), + DT_CLK(NULL, "dss_deshdcp_clk", "dss_deshdcp_clk"), DT_CLK(NULL, "gpio1_dbclk", "gpio1_dbclk"), DT_CLK(NULL, "gpio2_dbclk", "gpio2_dbclk"), DT_CLK(NULL, "gpio3_dbclk", "gpio3_dbclk"), @@ -306,7 +307,7 @@ static struct ti_dt_clk dra7xx_clks[] = { int __init dra7xx_dt_clk_init(void) { int rc; - struct clk *abe_dpll_mux, *sys_clkin2, *dpll_ck; + struct clk *abe_dpll_mux, *sys_clkin2, *dpll_ck, *dss_deshdcp_ck; ti_dt_clocks_register(dra7xx_clks); @@ -327,5 +328,10 @@ int __init dra7xx_dt_clk_init(void) if (rc) pr_err("%s: failed to configure GMAC DPLL!\n", __func__); + dss_deshdcp_ck = clk_get_sys(NULL, "dss_deshdcp_clk"); + rc = clk_prepare_enable(dss_deshdcp_ck); + if (rc) + pr_err("%s: failed to enable DESHDCP clock\n", __func__); + return rc; } -- 1.8.3.2 -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html