Hi, On Tue, Mar 18, 2014 at 12:18:41PM -0500, Felipe Balbi wrote: > hi, > > On Tue, Mar 18, 2014 at 12:11:10PM -0500, Felipe Balbi wrote: > > On Tue, Mar 18, 2014 at 05:04:47PM +0000, Mark Jackson wrote: > > > On 18/03/14 16:55, Felipe Balbi wrote: > > > > Hi Mark, > > > > > > > > I'm looking at the omap-serial driver and saw that you added rts-gpio > > > > binding in commit 4a0ac0f55b18dc297a87a85417fcf068658bf103 (OMAP: add > > > > RS485 support) but, as it turns out, gpio0_13 and gpio2_15 are both > > > > actual RTS signals. > > > > > > > > Instead of adding that extra GPIO handling, why didn't you just mux > > > > those signals as RTS and enable auto-RTS/auto-CTS feature ? > > > > > > > > It looks to me like that's highly unnecessary binding. > > > > > > I agree !! > > > > > > I think it was to allow delays pre- and post- sending the comms data. > > > > > > Several RS485 drivers require a "warm up" time before they will > > > transmit data correctly, and also need a "cool down" time to prevent > > > clipping of the last few bits of data. > > > > > > IIRC the built-in RTS handling did not allow for this. > > > > you might be right here. I can't find anywhere to write rts delays. > > Weird... digging TRM. > > hmm, you can change RTS value manually if you don't use auto-RTS. Just > write MCR BIT(1) to toggle that line. > > The "warm up" time you mention, however, can be coped with by means of > RX FIFO trigger level. TRM mentions that far end could send another byte > after RTS has been deasserted. So if we set RX trigger level to always > have room for one extra byte, then we will never loose data and the > "warm up" time is probably negligible. > > Am I missing something ? another small gem hidden in the TRM: "You must ensure that TCR[3:0] > TCR[7:4], whenever auto-RTS or software flow control is enabled to avoid a misoperation of the device. In FIFO interrupt mode with flow control, you have to also ensure that the trigger level to HALT transmission is greater or equal to receive FIFO trigger level (either TLR[7:4] or FCR[7:6]); otherwise, FIFO operation stalls." so there are quite a few things needed to get this working properly. -- balbi
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