On 2014-01-28 09:50, Tomi Valkeinen wrote: > On 2014-01-27 19:30, Ivaylo Dimitrov wrote: >> Hi Tomi, >> >> linux-next-20140124 DSS is broken on N900 - display stays black (there >> is some noise though). I booted the kernel with qemu and it gives the >> following warning: >> >> [ 0.623779] DSS: set fck to 172800000 >> [ 0.624237] ------------[ cut here ]------------ >> [ 0.624298] WARNING: CPU: 0 PID: 1 at >> drivers/video/omap2/dss/dss.c:497 dss_set_fck_rate+0x68/0x8c() >> [ 0.624359] clk rate mismatch: 288000000 != 172800000 > > That says that the omapdss tries to set the func clock to 172.8 MHz, but > after setting the rate, the clock is at 288 MHz. > > I just hit the same warning with beagle-xm yesterday, with v3.13-rc6 + > DSS device tree patches, although it might be a different thing. I see > that the actual clock is lower than what omapdss tries to set, you have > the other way around. > > The beagle-xm issue is related to a clk-divider fix I have sent some > time ago: > > http://mid.gmane.org/1383736008-22764-1-git-send-email-tomi.valkeinen@xxxxxx I made a somewhat hacky quickfix for beagle. Applying that and the clk-divider from the link above makes things work for me. However, as I said, the issue with n900 might be different, but it'd be interesting to hear if it has any effect. Tomi
From f633a151a01b06a7b86107d93f9f53e05601c02c Mon Sep 17 00:00:00 2001
From: Tomi Valkeinen <tomi.valkeinen@xxxxxx>
Date: Tue, 28 Jan 2014 10:19:07 +0200
Subject: [PATCH] OMAPDSS: DSS: fclk rate rounding test
---
drivers/video/omap2/dss/dss.c | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/drivers/video/omap2/dss/dss.c b/drivers/video/omap2/dss/dss.c
index 9009f62defd0..de35be6d6e20 100644
--- a/drivers/video/omap2/dss/dss.c
+++ b/drivers/video/omap2/dss/dss.c
@@ -473,8 +473,22 @@ bool dss_div_calc(unsigned long pck, unsigned long fck_min,
fckd_stop = max(DIV_ROUND_UP(prate * m, fck_hw_max), 1ul);
for (fckd = fckd_start; fckd >= fckd_stop; --fckd) {
+ unsigned long rfclk;
fck = prate / fckd * m;
+ /* do we get the right rate with this? */
+ rfclk = clk_round_rate(dss.dss_clk, fck);
+
+ if (rfclk != fck) {
+ /* no we don't. try rounding the other way */
+ fck += 1;
+
+ rfclk = clk_round_rate(dss.dss_clk, fck);
+
+ if (rfclk != fck)
+ DSSERR("mismatch %lu != %lu\n", rfclk, fck);
+ }
+
if (func(fck, data))
return true;
}
--
1.8.3.2
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