For HSMMC2 and HSMMC3 set SDVSS to 1.8V in HCTL before enabling the SDBP bit.
Signed-off-by: Jarkko Lavinen <jarkko.lavinen@xxxxxxxxx>
---
drivers/mmc/host/omap_hsmmc.c | 19 ++++++++++---------
1 files changed, 10 insertions(+), 9 deletions(-)
diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c
index a134f76..4bc25c0 100644
--- a/drivers/mmc/host/omap_hsmmc.c
+++ b/drivers/mmc/host/omap_hsmmc.c
@@ -1197,15 +1197,16 @@ static int omap_mmc_suspend(struct platform_device *pdev, pm_message_t state)
}
if (!(OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET)) {
- OMAP_HSMMC_WRITE(host->base, HCTL,
- OMAP_HSMMC_READ(host->base, HCTL)
- & SDVSCLR);
- OMAP_HSMMC_WRITE(host->base, HCTL,
- OMAP_HSMMC_READ(host->base, HCTL)
- | SDVS30);
- OMAP_HSMMC_WRITE(host->base, HCTL,
- OMAP_HSMMC_READ(host->base, HCTL)
- | SDBP);
+ u32 hctl = OMAP_HSMMC_READ(host->base, HCTL) &
+ SDVSCLR;
+
+ if (host->id == OMAP_MMC1_DEVID)
+ hctl |= SDVS30;
+ else
+ hctl |= SDVS18;
+
+ OMAP_HSMMC_WRITE(host->base, HCTL, hctl);
+ OMAP_HSMMC_WRITE(host->base, HCTL, hctl | SDBP);
}
mmc_omap_fclk_state(host, OFF);
--
1.5.4.3
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