The only way to ensure write posting to L4 bus is to do a read back of the same register right after the write. This seems to be mostly needed in interrupt handlers to avoid causing spurious interrupts. The earlier fix has been to mark the L4 bus as strongly ordered memory, which solves the problem, but causes performance penalties. Similar fixes may be needed in other interrupt handlers too. Signed-off-by: Tony Lindgren <tony@xxxxxxxxxxx> diff --git a/drivers/dsp/bridge/hw/hw_mbox.c b/drivers/dsp/bridge/hw/hw_mbox.c index 7055259..96b5680 100644 --- a/drivers/dsp/bridge/hw/hw_mbox.c +++ b/drivers/dsp/bridge/hw/hw_mbox.c @@ -251,5 +251,20 @@ HW_STATUS HW_MBOX_EventAck(const u32 baseAddress, const HW_MBOX_Id_t mailBoxId, MLBMAILBOX_IRQSTATUS___0_3WriteRegister32(baseAddress, (u32)userId, (u32)irqStatusReg); + /* + * FIXME: Replace all this custom register access with standard + * __raw_read/write(). + * + * FIXME: Replace all interrupt handlers with standard linux style + * interrupt handlers. + * + * FIXME: Replace direct access to PRCM registers with omap standard + * PRCM register access. + * + * Do a read back for the irq status to ensure the write above gets + * posted to avoid spurious interrupts. + */ + MLBMAILBOX_IRQSTATUS___0_3ReadRegister32(baseAddress, (u32)userId); + return status; } -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
