> On Wed, 2008-08-06 at 07:28 -0500, Woodruff, Richard wrote: > > > The code need to execute in a non-cached region. > > > > I don't think there is any guarantee that dirty cache line won't be > > evicted to SDRAM even if your code uses uncached memory only. The CPU > > is > > allowed to do speculative reads from the normal cached memory and > > these > > reads may force a dirty cache line to be written back to memory. You > > may > > need to do at least a cache clean operation (invalidate not necessary). > > I hope that is not necessary. Probably not but need to check internally as well. > As I indicated the code in question is small assembly dealing with > hardware registers for clock and power. > > This code at one point did make sure use barriers at entry which > hopefully stop the ARM from being smart. Also things like speculative > access at the AXI were turned off. You would need a DSB at the beginning to drain the write buffer (among other things) > And perhaps you even make my point in 'The CPU is allowed to do > speculative reads from normal-cached-memory'. > !! I don't want some speculative branch prediction to fetch > from who knows where when I've temporally shut off the memory > controller !! If you have a DMB at the end of your code, this ensures that all memory accesses after the DMB (i.e. accesses to the SDRAM) are visible after accesses before the barrier (i.e. the enabling of the SDRAM controller). -- Catalin -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
